M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 379

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 355 of 587
Figure 22.27
(1) When the base timer is not reset
(2) When the base timer is reset by matching the GiPO0 register
Base timer i
Count source of
base timer
Base timer value
Read value from
the GiBT register
OUTCi_ j pin
POijR bit in registers
IIO0IR to IIO11IR
Base timer i
Count source of
base timer
Base timer value
Read value from
the GiBT register
OUTCi_j pin
POijR bit
in the IIOkIR register
i = 1, 2; j = 1 to 7; k = 0 to 5, 7 to 11
m: Setting value of the GiPOj register (0000h to FFFFh); p: Setting value of the GiPO0 register (0001h to FFFDh)
The above applies under the following conditions:
- Group 1: In the G1BCR1 register, bits RST2 and RST1 are set to 01b, and bits UD1 and UD0 are set to 00b (counter increment mode)
- Group 2: In the G2BCR1 register, bits RST2 to RST0 are set to 010b (Base timer is reset by matching the G2PO0 register)
- In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted)
- m < p + 2
i = 1, 2; j = 0 to 7
m: Setting value of the GiPOj register (0000h to FFFFh)
The above applies under the following conditions:
- Group 1: In the G1BCR1 register, bits RST2 and RST1 are set to 00b and bits UD1 and UD0 are set to 00b (counter increment mode)
- Group 2: In the G2BCR1 register, bits RST2 to RST0 are set to 000b (Base timer is not reset by matching the G2PO0 register)
- In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted)
Single-Phase Waveform Output Mode Operation
FFFFh
0000h
0000h
"H"
"H"
"L"
"L"
1
0
p+1
1
0
m
m
0000
0000
0000
0000
0001
0001
0001
0001
0002
0002
0002
0002
fBTi
fBTi
m
m
Match
Match
m
m
m
m
m+1
m+1
m+1
m+1
m+2
m+2
22. Intelligent I/O (Waveform Generation Function)
m+2
m+2
p + 2 - m
65536 - m
FFFE FFFF 0000
fBTi
Set to 0 by a program
Set to 0 by a program
p
fBTi
FFFE FFFF 0000
p
p+1
p+1
Reset
0000
0000
0001
0001
0001
0001
0002
0002
0002
0002
0003
0003
0003
0003