M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 412

IC M32C/87 MCU FLASH 144LQFP

M3087BFLBGP#U5

Manufacturer Part Number
M3087BFLBGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M3087BFLBGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 388 of 587
Figure 22.53
Figure 22.54
The above applies under the following conditions:
- The STPS bit in the G1MR register is set to 0 (1 stop bit)
- The PRYE bit in the G1MR register is set to 0 (parity disabled)
- The UFORM bit in the G1MR register is set to 0 (LSB first)
- The INV bit in registers G1POCR0 to G1POCR7 is set to 0 (output not inverted)
The SIO1RR bit
Internal receive
Internal receive
The above applies under the following conditions:
- The STPS bit in the G1MR register is set to 0 (1 stop bit)
- The PRYE bit in the G1MR register is set to 0 (parity disabled)
- The UFORM bit in the G1MR register is set to 0 (LSB first)
- The INV bit in registers G1POCR0 to G1POCR7 is set to 0 (output not inverted)
- The IRS bit in the G1MR register is set to 0 (no data in the G1TB register)
Internal transmit
clock
ISTXD1 pin
TI bit in the G1CR
register
TXEPT bit in the
G1CR register
SIO1TR bit in the
IIO3IR register
Base timer 1
ISRXD1 pin
ISRXD1 pin
The RI bit
clock
clock
Transmit Operation in Group 1 UART Mode
Receive Operation in Group 1 UART Mode
0000h
n + 1
"H"
"L"
1
0
1
0
"H"
"L"
1
0
1
0
1
0
Synchronization
ST
ST
Set data in the G1TB register
D0 D1 D2 D3 D4 D5 D6 D7
D0
Start Bit (ST)
D1
2 (n + 2)
D2
fBT1
Set to 0 by a program
D3
Cycle
D4
D5
SP
D6
D7
SIO1RR bit: The bit in the IIO2IR register
RI bit: The bit in the G1CR register
SP
ST
Set data in the G1TB register
D0 D1 D2 D3 D4 D5 D6 D7
D0
Set to 0 by a program
Read the G1RB register
ST
D0
D1
D2
SP

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