M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 274

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 250 of 587
Figure 17.25
17.1.3.1 Detecting Start Condition and Stop Condition
17.1.3.2 Start Condition or Stop Condition Output
Table 17.13
Output from pins SCLi and
SDAi
Timing to generate start
condition and stop condition
interrupt requests
The MCU detects the start condition and stop condition. The start condition detection interrupt request is
generated when the SDAi (i = 0 to 4) pin level changes from high (“H”) to low (“L”) while the SCLi pin level is
held “H”. The stop condition detection interrupt request is generated when the SDAi pin level changes from “L”
to “H” while the SCLi pin level is held “H”.
The start condition detection interrupt shares the Interrupt Control Register and interrupt vector with the stop
condition detection interrupt. The BBS bit in the UiSMR register determines which interrupt is requested.
The start condition is generated when the STAREQ bit in the UiSMR4 register (i = 0 to 4) is set to 1 (start).
The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to 1 (start).
The stop condition is generated when the STPREQ bit in the UiSMR4 is set to 1 (start).
The following is the procedure to output the start condition, restart condition, or stop condition.
Table 17.13 and Figure 17.26 show functions of the STSPSEL bit.
6 cycles < setup time
6 cycles < hold time
(1) Set the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the UiSMR4 register to 1 (start/stop condition generation circuit selected).
(start condition)
(stop condition)
Function
i=0 to 4
NOTE:
Start Condition or Stop Condition Detection
STSPSEL Bit Function
1. These are cycles of the main clock oscillation frequency f(XIN).
SDAi
SDAi
SCLi
(1)
(1)
Output the serial clock and data.
Output of the start condition or stop
condition is controlled by software
utilizing port functions. (The start
condition and stop condition are not
automatically generated by hardware)
When start condition and stop condition
are detected
STSPSEL = 0
Setup time
Output of the start condition or stop
condition is controlled by the status of bits
STAREQ, RSTAREQ, and STPREQ.
When start condition and stop condition
generation are completed
17. Serial Interfaces (UART0 to UART4)
Hold time
STSPSEL = 1