M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 181

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 157 of 587
14.5
Figure 14.4
14.6
The chain transfer can be selected with the CHAIN bit in MOD.
The chain transfer is performed as follows.
Figure 14.4 shows the relocatable vector and DMACII index when using the chain transfer.
For the chain transfer, the relocatable vector table must be located in the RAM.
The end-of-transfer interrupt can be selected with the INTE bit in MOD. Set the starting address of the end-of-
transfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt occurs when COUNT reaches zero.
(1) Transfer occurs in response to an interrupt request from a peripheral function and is performed according to
(2) When COUNT reaches zero, the interrupt vector in (1) is replaced with the address written in CADR1 and
(3) When the next DMACII transfer request is generated, the transfer is performed according to the contents of
Chain Transfer
End-of-Transfer Interrupt
the contents of the DMACII index at the address specified by the interrupt vector. For one transfer request,
either a single transfer or burst transfer selected by the BRST bit in MOD occurs.
CADR0. The end-of-transfer interrupt occurs after the replacement, if the INTE bit in MOD is set to 1.
the DMACII index specified by the interrupt vector which has been replaced in (2).
Relocatable
Vector
DMACII index (a)
DMACII index (b)
Relocatable Vector and DMACII Index When using the Chain Transfer
INTB
BASE (a)
(CADR1,
CADR0)
BASE (b)
(CADR1,
CADR0)
BASE (b)
BASE (c)
RAM
Interrupt vector of the peripheral function triggering
DMACII request. Default value is BASE (a).
When COUNT reaches zero, the interrupt vector
is replaced wtih BASE (c).
When the next request occurs, a transfer starts
according to the contents of the DMACII index at
BASE (b).
When COUNT reaches zero, the above interrupt
vector is replaced with BASE (b), which is the
address written in CADR1 and CADR0.
14. DMACII