M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 268

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 244 of 587
Table 17.8
i = 0 to 4
UiMR
UiSMR
UiSMR2
UiSMR3
UiSMR4
Register
Register Settings in I
SMD2 to SMD0
CKDIR
IOPOL
IICM
ABC
BBS
7 to 3
IICM2
CSC
SWC
ALS
STC
SWC2
SDHI
SU1HIM
SSE
CKPH
DINC, NODC, ERR
DL2 to DL0
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
Bit
Set to 010b
Set to 0
Set to 0
Set to 1
Select an arbitration lost detect timing Disabled
Bus busy flag
Set to 00000b
See Tables 17.10 and 17.11 Functions in I
Set to 1 to enable clock
synchronization
Set to 1 to hold an “L” signal output from SCLi at the falling edge of the ninth
bit of the serial clock
Set to 1 to abort an SDAi output when
detecting the arbitration lost
Set to 0
Set to 1 to forcibly make a signal output from SCL an “L”
Set to 1 to disable SDA output
Set to 0
Set to 0
See Tables 17.10 and 17.11 Functions in I
Set to 0
Set SDAi digital delay value
Set to 1 to generate the start
condition
Set to 1 to generate the restart
condition
Set to 1 to generate the stop
condition
Set to 1 when using a condition
generation function
Select ACK or NACK
Set to 1 to output ACK data
Set to 1 to enable SCL output stop
when detecting the stop condition
Set to 0
2
C Mode (1/2)
Master
Setting Value
17. Serial Interfaces (UART0 to UART4)
Set to 1
Set to 0
Set to 0
Set to 1 to initialize UARTi by
detecting the start condition
Set to 0
Set to 0
Set to 1 to hold an “L” signal output
from SCLi at the falling edge of the
ninth bit of the serial clock
2
2
C Mode
C Mode
Slave