M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 12

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.
13.
14.
11.6
11.7
11.8
11.9
11.10
11.11
13.1
13.2
13.3
14.1
14.2
14.3
14.4
14.5
14.6
11.5.2
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
11.6.9
11.11.1 IIOiIE Register ................................................................................................................................. 131
11.11.2 IIOiIR Register ................................................................................................................................. 131
11.11.3 IIOiIC (CANjIC) Register ................................................................................................................ 131
13.1.1
13.1.2
13.1.3
13.1.4
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.3.1
14.3.2
14.3.3
14.4.1
14.4.2
14.4.3
Watchdog Timer .......................................................................................................................... 134
DMAC ......................................................................................................................................... 138
DMACII ....................................................................................................................................... 151
Interrupt Request Acknowledgement .................................................................................................... 113
INT Interrupt ......................................................................................................................................... 122
NMI Interrupt ........................................................................................................................................ 126
Key Input Interrupt ................................................................................................................................ 126
Address Match Interrupt ....................................................................................................................... 127
Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/Receive Interrupts,
and INT6 to INT8 Interrupts .................................................................................................................. 128
Transfer Cycles ..................................................................................................................................... 148
DMA Transfer Time ............................................................................................................................. 149
Channel Priority and DMA Transfer Timing ........................................................................................ 149
DMACII Settings .................................................................................................................................. 151
DMACII Performance ........................................................................................................................... 155
Transfer Data ......................................................................................................................................... 155
Transfer Modes ..................................................................................................................................... 156
Chain Transfer ....................................................................................................................................... 157
End-of-Transfer Interrupt ...................................................................................................................... 157
Relocatable Vector Table ................................................................................................................. 110
I Flag and IPL ................................................................................................................................... 113
Interrupt Control Registers and RLVL Register ............................................................................... 113
Interrupt Sequence ............................................................................................................................ 117
Interrupt Response Time .................................................................................................................. 118
IPL Change when Interrupt Request is Acknowledged .................................................................... 119
Saving a Register .............................................................................................................................. 119
Returning from Interrupt Routine ..................................................................................................... 120
Interrupt Priority ............................................................................................................................... 120
Interrupt Priority Level Decision Circuit .......................................................................................... 120
Effect of Source and Destination Addresses .................................................................................... 148
Effect of the DS Register .................................................................................................................. 148
Effect of Software Wait State ........................................................................................................... 148
Effect of the RDY Signal .................................................................................................................. 148
RLVL Register ................................................................................................................................. 151
DMACII Index ................................................................................................................................. 153
Interrupt Control Register for the Peripheral Function .................................................................... 155
Relocatable Vector Table for the Peripheral Function ..................................................................... 155
IRLT Bit in the IIOiIE Register (i = 0 to 11) .................................................................................... 155
Memory-to-memory Transfer ........................................................................................................... 155
Immediate Data Transfer .................................................................................................................. 156
Calculation Transfer ......................................................................................................................... 156
Single Transfer ................................................................................................................................. 156
Burst Transfer ................................................................................................................................... 156
Multiple Transfer .............................................................................................................................. 156
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