M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 407

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 383 of 587
Figure 22.49
Transmit/receive operation starts by writing data to the G1TB Register.
Read the G1RB register after the receive operation is completed.
k = 2, 3
NOTE:
1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1
when an interrupt request is generated in the same register (Interrupt does not occur).
Continued from to Register Settings in Group 1 Clock Synchonous Mode (1/2 )
< When count source in base timer is changed >
G1CR register: TE bit = 0
G1MR register:
G1ERC register = 00100000b
G1BCR1 register = 00000010b
G1BCR0 register:
G1BCR1 register: BTS bit = 1
IIOkIR register = 00h
IIOkIE register: IRLT bit = 1
IIO3IE register: SIO1TE bit = 1
IIO2IE register: SIO1RE bit = 1
IIOkIC register: bits ILVL2 to ILVL0
Pin settings in Function Select Registers
I flag = 1
G1CR register: TE bit = 1
Register Settings in Group 1 Clock Synchronous Mode (2/2)
Wait time (1 serial clock cycle)
bits GMD1 and GMD0 = 01b
CKDIR bit
bits 5 to 3 = 000b
UFORM bit
IRS bit
bits BCK1 and BCK0 = 11b
bits DIV4 to DIV0
IT bit = 0
End initial setting
RE bit = 0
IPOL bit
OPOL bit
IR bit = 0
RE bit = 1
(1)
Transmit operation disabled
Receive operation disabled
ISRXD input polarity invert bit
ISTXD output polarity invert bit
Clock synchronous mode
Clock select bit
Bit order select bit
Transmit interrupt source select bit
Base timer reset
Select f1 as count source
Count source divide ratio select bits
Base timer count starts
Interrupt not requested
Interrupt request is used for
interrupt
Group 1 transmit interrupt enabled
Group 1 receive interrupt enabled
Interrupt priority level select bit
Interrupt not requested
Interrupt enabled
Transmit operation enabled
Receive operation enabled
Do not set at the same time.
Set bits SIO1TE and SIO1RE to 1
after setting the IRLT bit to 1.