M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 290

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 266 of 587
Figure 17.33
(1) Transmit operation
(2) Receive operation
Internal transmit
clock
TE bit in the
UiC1 register
TI bit in the UiC1
register
TXDi output
Parity error signal
sent back from
receiving device
Signal line level
TXEPT bit in the
UiC0 register
IR bit in the
SiTIC register
Internal receive
clock
RE bit in the
UiC1 register
Transmit
waveform sent by
transmitting device
TXDi ouput
Signal line level
RI bit in the
UiC1 register
IR bit in the SiRIC
register
The above applies under the following conditions:
The above applies under the following conditions:
i = 0 to 4
TC =
NOTES:
1. Transmit operation is started when UiBRG overflows after data is set in the UiTB register in the indicated timing.
2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity error signal from the
3. Because pins TXDi and RXDi are connected, a composite waveform consisting of transmit waveform from the transmitting device and parity error
4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated at the transmit completion)
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
receiving device, is generated.
signal from the TXDi pin, is generated.
16( m+ 1)
fj
SIM Interface Operation
(2)
(3)
“H”
“L”
“H”
“L”
1
0
1
0
1
0
1
0
1
0
1
0
1
0
fj: f1, f8, f2n
m: setting value of the UiBRG register (00 to FF)
Start bit
Start bit
ST
ST
ST
ST
(4)
TC
TC
D0
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
D1 D2 D3 D4 D5 D6
"L" level is sent back from the SIM card since parity error has occurred
"L" level is sent back from the SIM card since parity error has occurred
Data is set in UiTB register
D7
D7
D7
D7
Parity bit
Set to 0 by an interrupt request acknowledgement or by a program
Set to 0 by an interrupt request acknowledgement or by a program
Parity bit
Stop bit
P
P
P
P
Stop bit
SP
SP
SP
SP
(note 1)
Detect the level in interrupt routine
ST
ST
ST
ST
Read from the UiRB register
Data is transfer from UiTB register
to UARTi transmit shift register
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
17. Serial Interfaces (UART0 to UART4)
D7
D7
D7
D7
P
P
P
P
SP
SP
SP
SP