M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 321

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 297 of 587
Figure 18.4
A/D0 Control Register 2
b7
0 0
b6 b5 b4
NOTES:
1. If the AD0CON2 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. In the 100-pin package, do not set to 01b.
3. Set to 00b or 01b in memory expansion mode and microprocessor mode.
b3
b2
AD0CON2 Register
b1
b0
Bit Symbol
(b4-b3)
(b7-b6)
APS0
APS1
TRG0
SMP
Symbol
AD0CON2
−
−
(1)
A/D conversion method
select bit
Analog input port
select bits
Unimplemented.
Write 0. Read as undefined value.
External trigger source select bit
Reserved bits
(3)
Bit Name
Address
0394h
0: Without sample and hold
1: With sample and hold
When the MSS bit in the AD0CON3 register = 0
b2 b1
0 0: AN_0 to AN_7, ANEX0, ANEX1
0 1: AN15_0 to AN15_7
1 0: AN0_0 to AN0_7
1 1: AN2_0 to AN2_7
When the MSS bit in the AD0CON3 register = 1
0: ADTRG selected
1: Timer B2 interrupt request of the three-phase
Set to 0.
Read as undefined value.
Set to 01b.
motor control timer function (after the ICTB2
register completes counting) selected
Function
(2)
After Reset
XX0X X000b
18. A/D Converter
RW
RW
RW
RW
RW
RW
−