M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 375

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 351 of 587
Table 22.6
NOTES:
P6_4
P7_0
P7_0
P7_1
P7_1
P7_3
P7_4
P7_5
P7_6
P7_7
P8_1
P9_2
P11_0
P11_1
P11_2
P11_3
P13_0
P13_1
P13_2
P13_3
P13_4
P13_5
P13_6
P13_7
P14_0
P14_1
P14_2
P14_3
1. Set registers PS0 to PS3, PS5, PS7, and PS8 after setting the other registers.
2. This port is provided in the 144-pin package only.
3. P7_0 and P7_1 are N-channel open drain output ports.
4. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not
Port
(3)
(3)
(3)
(3)
generate an interrupt or a DMA or DMACII transfer between these two instructions.
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
OUTC2_1
OUTC1_6
OUTC2_0
OUTC1_7
OUTC2_2
OUTC1_0
OUTC1_1
OUTC1_2
OUTC1_3
OUTC1_4
OUTC1_5
OUTC2_0
OUTC1_0
OUTC1_1
OUTC1_2
OUTC1_3
OUTC2_4
OUTC2_5
OUTC2_6
OUTC2_3
OUTC2_0
OUTC2_2
OUTC2_1
OUTC2_7
OUTC1_4
OUTC1_5
OUTC1_6
OUTC1_7
Pin Settings for Waveform Generation Function
Function
−
PSE1_0 = 0
−
PSE1_1 = 0
−
−
−
−
PSE1_6 = 0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PSE1 Register
−
PSD1_0 = 1
PSD1_0 = 0
PSD1_1 = 1
PSD1_1 = 0
−
PSD1_4 = 0
−
PSD1_6 = 1
PSD1_7 = 0
PSD2_1 = 0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PSD1 Register
22. Intelligent I/O (Waveform Generation Function)
−
PSC_0 = 1
PSC_0 = 1
PSC_1 = 1
PSC_1 = 1
PSC_3 = 1
PSC_4 = 1
PSC_5 = 0
PSC_6 = 0
−
PSC2_1 = 1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PSC, PSC2
Bit Setting
Registers
PSL0_4 = 1
PSL1_0 = 0
PSL1_0 = 0
PSL1_1 = 0
PSL1_1 = 0
PSL1_3 = 0
PSL1_4 = 0
PSL1_5 = 1
PSL1_6 = 0
PSL1_7 = 1
PSL2_1 = 1
PSL3_2 = 1
PSL5_0 = 0
PSL5_1 = 0
PSL5_2 = 0
PSL5_3 = 0
PSL7_0 = 0
PSL7_1 = 0
PSL7_2 = 0
PSL7_3 = 0
PSL7_4 = 0
PSL7_5 = 0
PSL7_6 = 0
PSL7_7 = 0
−
−
−
−
PSL0 to PSL3,
PSL5, PSL7
Registers
PS0_4 = 1
PS1_0 = 1
PS1_0 = 1
PS1_1 = 1
PS1_1 = 1
PS1_3 = 1
PS1_4 = 1
PS1_5 = 1
PS1_6 = 1
PS1_7 = 1
PS2_1 = 1
PS3_2 = 1
PS5_0 = 1
PS5_1 = 1
PS5_2 = 1
PS5_3 = 1
PS7_0 = 1
PS7_1 = 1
PS7_2 = 1
PS7_3 = 1
PS7_4 = 1
PS7_5 = 1
PS7_6 = 1
PS7_7 = 1
PS8_0 = 1
PS8_1 = 1
PS8_2 = 1
PS8_3 = 1
PS5, PS7, PS8
Registers
PS0 to PS3,
(1)(4)