M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 189

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 165 of 587
Figure 15.7
Timer Ai Mode Register (i = 0 to 4)(One-Shot Timer Mode)
b7
b6 b5 b4
NOTES:
0
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the
1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN
CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
pin).
The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj
(j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow).
b3
b2
TA0MR to TA4MR Registers in One-Shot Timer Mode
0
b1
1
b0
0
Bit Symbol
TMOD0
TMOD1
TCK0
TCK1
MR1
MR2
MR3
(b2)
Symbol
TA0MR to TA4MR
−
Operating mode select bits
Reserved bit
External trigger select bit
Trigger select bit
Set to 0 in one-shot timer mode
Count source select bits
Bit Name
Address
0356h, 0357h, 0358h, 0359h, 035Ah
(1)
b7 b6
0 0: f1
0 1: f8
1 0: f2n
1 1: fC32
b1 b0
1 0: One-shot timer mode
Set to 0
0: Falling edge of signal applied to the TAiIN pin
1: Rising edge of signal applied to the TAiIN pin
0: The TAiOS bit enabled
1: Selected by bits TAiTGH and TAiTGL
(2)
Function
After Reset
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
15. Timer A