M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 447

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 423 of 587
Figure 23.17
23.1.14 CANi Error Interrupt Status Register (CiEISTR Register) (i = 0, 1)
23.1.14.1 BOIS Bit
23.1.14.2 EPIS Bit
23.1.14.3 BEIS Bit
CANi Error Interrupt Status Register (i = 0, 1)
b7 b6 b5 b4
When using the CAN interrupt, the CiEISTR register determines an error interrupt source.
Bits BOIS, EPIS, and BEIS are not automatically set to 0 (interrupt not requested) even if the interrupt is
acknowledged. Set these bits to 0 by a program.
Use the MOV instruction to set each bit in the CiEISTR register to 0. Write a 0 to the bit which is to set to 0, and
write a 1 to the bit which is to remain unchanged.
Refer to 23.4 CAN Interrupts for details.
The BOIS bit becomes 1 when the CAN module is placed in a bus-off state.
NOTE:
The EPIS bit becomes 1 when the CAN module is placed in an error passive state.
NOTE:
The BEIS bit becomes 1 when a CAN bus error is detected.
NOTE:
NOTES:
1. Regardless of whether the BOIM bit in the CiEIMKR register is set to 0 (interrupt request masked) or 1
1. Regardless of whether the EPIM bit in the CiEIMKR register is set to 0 (interrupt request masked) or 1
1. Regardless of whether the BEIM bit in the CiEIMKR register is set to 0 (interrupt request masked) or 1
1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the
2. Set each bit to 0 by a program. Writing a 1 has no effect.
(interrupt request enabled), the BOIS bit becomes 1 when the CAN module becomes a bus-off state.
(interrupt request enabled), the EPIS bit becomes 1 when the CAN module becomes an error-passive
state.
(interrupt request enabled), the BEIS bit becomes 1 when the CAN bus error is detected.
clock to the CAN module.
b3
For example: To set the BOIS bit in CAN0 to 0
mov.b #006h, C0EISTR
b2
C0EISTR and C1EISTR Registers
b1
b0
Bit Symbol
(b7-b3)
BOIS
EPIS
BEIS
Symbol
C0EISTR
C1EISTR
−
Bus-off interrupt
status bit
Error-passive interrupt
status bit
CAN bus-error interrupt
status bit
Unimplemented.
Write 0. Read as undefined value.
Bit Name
Address
0215h
0295h
0: Interrupt not requested
1: Interrupt requested
0: Interrupt not requested
1: Interrupt requested
0: Interrupt not requested
1: Interrupt requested
Function
(2)
(2)
(2)
After Reset
XXXX X000b
XXXX X000b
23. CAN Module
(1)
RW
RW
RW
RW
−