M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 162

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 138 of 587
13. DMAC
DMAC allows data to be sent to and from memory without involving the CPU. The M32C/87 Group (M32C/87,
M32C/87A, M32C/87B) has four DMAC channels. DMAC transfers an 8- or 16-bit data from a source address to a
destination address for each transfer request. DMA0 and DMA1 must be prioritized when using DMAC. DMA2 and
DMA3 share the registers with the high-speed interrupts. The high-speed interrupts cannot be used when three or more
DMAC channels are used.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. DMAC
employing the cycle-steal method enables a high-speed operation from a transfer request to a completion of 16-bit
(word) or 8-bit (byte) data transfer.
Figure 13.1 shows a mapping of DMAC-associated registers. Table 13.1 lists specifications of DMAC. Figures 13.2 to
13.6 show DMAC-associated registers. Figures 13.7 and 13.8 show register settings.
Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to set the registers.
To set registers DCT2, DCT3, DRC2, DRC3, DMA2, and DMA3, set the B flag to 1 (register bank 1) and write to
registers R0 to R3, A0, and A1 with the MOV instruction.
To set registers DSA2 and DSA3, set the B flag to 1 and write to registers SB and FB with the LDC instruction.
To set registers DRA2 and DRA3, write to registers SVP and VCT with the LDC instruction.
Figure 13.1
DMAC-Associated Registers
When three or more DMAC channels are used,
the register bank 1 is employed as DMAC registers.
NOTE:
DMA2(A0)
DMA3(A1)
DSA2(SB)
DSA3(FB)
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
1. These registers are used for repeat transfer, not for single transfer.
DRC2(R2)
DRC3(R3)
DCT2(R0)
DCT3(R1)
DRC0
DRC1
DCT0
DCT1
DMD0
DMD1
Register Mapping for DMAC
DMA mode register 0
DMA mode register 1
DMA0 transfer count register
DMA1 transfer count register
DMA0 transfer count reload register
DMA1 transfer count reload register
DMA0 memory address register
DMA1 memory address register
DMA0 SFR Address register
DMA1 SFR Address register
DMA0 memory address reload register
DMA1 memory address reload register
DMA2 transfer count register
DMA3 transfer count register
DMA2 transfer count reload register
DMA3 transfer count reload register
DMA2 memory address register
DMA3 memory address register
DMA2 SFR Address register
DMA3 SFR Address register
(1)
(1)
(1)
(1)
(1)
(1)
When three or more DMAC channels are used,
the high-speed interrupt registers are employed as DMAC
registers.
DRA2(SVP)
DRA3(VCT)
When using DMA2 and DMA3, use the CPU registers shown in
parentheses ( ).
SVF
Flag save register
DMA2 memory address reload register
DMA3 memory address reload register
(1)
(1)
13. DMAC