M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 276

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 252 of 587
17.1.3.3 Arbitration
17.1.3.4 Serial Clock
17.1.3.5 SDA Output
The ABC bit in the UiSMR register (i = 0 to 4) determines an update timing of the ABT bit in the UiRB
register. At the rising edge of the clock input to the SCLi pin, the MCU determines whether a transmit data
matches data input to the SDAi pin.
When the ABC bit is set to 0 (update per bit), the ABT bit becomes 1 (detected - arbitration is lost) as soon as a
data discrepancy is detected. The ABT bit remains 0 (not detected - arbitration is won) if not detected. When the
ABC bit is set to 1 (update per byte), the ABT bit becomes 1 at the falling edge of the ninth cycle of the serial
clock if discrepancy is ever detected. When the ABT bit is updated per byte, set the ABT bit to 0 after an ACK
detection in the first byte data is completed. Then the next byte data transfer can be started.
When the ALS bit in the UiSMR2 register is set to 1 (SDAi output stopped) and the ABT bit becomes 1
(detected - arbitration is lost), the SDAi pin is placed in a high-impedance state simultaneously.
The serial clock is used to transmit and receive data as is shown in Figure 17.24.
By setting the CSC bit in the UiSMR2 register to 1 (clock synchronized), an internally generated clock (internal
SCLi) is synchronized with the external clock applied to the SCLi pin. If the CSC bit is set to 1, the internal
SCLi becomes low (“L”) when the internal SCLi is held high (“H”) and the external clock applied to the SCLi
pin is at the falling edge. The contents of the UiBRG register are reloaded and a counting for “L” period is
started. When the external clock applied to SCLi pin is held “L” and then the internal SCLi changes “L” to “H”,
the UiBRG counter stops. The counting is resumed when the clock applied to SCLi pin becomes “H”. The
UARTi serial clock is equivalent to logical AND operation of the internal SCLi and the clock signal applied to
the SCLi pin.
The serial clock is synchronized between a half cycle before the falling edge of the first bit and the rising edge
of the ninth bit of the internal SCLi. Select the internal clock as the serial clock while the CSC bit is set to 1.
The SWC bit in the UiSMR2 register determines whether an output signal from the SCLi pin is held “L” at the
falling edge of the ninth cycle of the serial clock or not.
When the SCLHI bit in the UiSMR4 register is set to 1 (SCLi output stopped), a SCLi output stops as soon as
the stop condition is detected (the SCLi pin is in a high-impedance state).
When the SWC2 bit in the UiSMR2 register is set to 1 (SCLi pin is held “L”), the SCLi pin forcibly outputs an
“L” even in the middle of transmitting and receiving. The fixed “L” output from the SCLi pin is cancelled by
setting the SWC2 bit to 0 (serial clock), and then the serial clock inputs to or outputs from the SCLi pin.
When the CKPH bit in the UiSMR3 register is set to 1 (clock delay) and the SWC9 bit in the UiSMR4 register
is set to 1 (SCLi pin is held “L” after receiving 9th bit), an output signal from the SCLi pin is held “L” at the
next falling edge to the ninth bit of the clock. The fixed “L” output from the SCLi pin is cancelled by setting the
SWC9 bit to 0 (no wait state/release wait state).
Values set in bits 7 to 0 (D7 to D0) in the UiTB register are output in descending order from D7. The ninth bit
(D8) is ACK or NACK.
Set the default value of SDAi transmit output, while the IICM bit in the UiSMR register is set to 1 (I
and bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled).
Bits DL2 to DL0 in the UiSMR3 register determine no delay or delay of 2 to 8 UiBRG register count source
cycles are added to an SDAi output.
When the SDHI bit in the UiSMR2 register is set to 1 (SDA output stopped), the SDAi pin is forcibly placed in
a high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi serial clock. The ABT bit
in the UiRB register may become 1 (detected).
17. Serial Interfaces (UART0 to UART4)
2
C mode)