R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 101
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 101 of 1342
- Download datasheet (7Mb)
2.6
This LSI has major three processing states: the reset state, instruction execution state, and power-
down state.
Reset State: In this state the CPU is reset. The reset state is divided into the power-on reset state
and the manual reset.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and some registers
of on-chip peripheral modules are initialized. For details, see register descriptions for each section.
Instruction Execution State: In this state, the CPU executes program instructions in sequence.
The Instruction execution state has the normal program execution state and the exception handling
state.
Power-Down State: In a power-down state, the CPU halts operation and power consumption is
reduced. The power-down state is entered by executing a SLEEP instruction. This LSI supports
sleep mode for the power-down state.
Processing States
Instruction execution state
Reset/manual
reset clearance
From any state
when reset/manual
reset input
Figure 2.8 Processing State Transitions
Reset/manual
reset input
Sleep instruction execution
Interrupt occurence
Reset state
Rev.1.00 Dec. 13, 2005 Page 49 of 1286
Power-down state
Reset/manual
reset input
Section 2 Programming Model
REJ09B0158-0100
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