R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 619

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.3.1
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address.
To transfer data in word or in longword units, specify the address with word or longword address
boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary
must be set for the source address value. The initial value is undefined.
7
8
Channel Name
9
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA source address register
B7
DMA destination address
register B7
DMA transfer count register B7 TCRB7
DMA source address register
B8
DMA destination address
register B8
DMA transfer count register B8 TCRB8
DMA source address register
B9
DMA destination address
register B9
DMA transfer count register B9 TCRB9
DMA Source Address Registers 0 to 11 (SAR0 to SAR11)
R/W
R/W
31
—
15
—
R/W
R/W
30
—
14
—
R/W
R/W
29
—
13
—
R/W
R/W
28
—
12
—
R/W
R/W
Abbrev.
SARB7
DARB7
SARB8
DARB8
SARB9
DARB9
27
—
11
—
R/W
R/W
26
—
10
—
Power-on Reset
by PRESET/WDT/
H-UDI
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
25
—
—
9
R/W
R/W
24
—
—
Section 14 Direct Memory Access Controller (DMAC)
8
SAR
SAR
R/W
R/W
23
—
—
7
Manual Reset by
WDT/Multiple
Exceptions
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Rev.1.00 Dec. 13, 2005 Page 567 of 1286
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
Sleep by SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
R/W
R/W
19
—
—
3
REJ09B0158-0100
R/W
R/W
18
—
—
2
R/W
R/W
17
—
—
Module
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
1
R/W
R/W
16
—
—
0