R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1160
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 29 User Break Controller (UBC)
• CBR1
Rev.1.00 Dec. 13, 2005 Page 1108 of 1286
REJ09B0158-0100
Bit
31
30
29 to 24
23 to 16
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Bit Name
MFE
AIE
MFI
AIV
MFE
R/W
DBE
R/W
31
15
0
0
R/W
R/W
AIE
30
14
0
0
R/W
R/W
29
13
SZ
1
0
Initial
Value
0
0
100000
All 0
R/W
R/W
28
12
0
0
ETBE
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
R/W
MFI
R/W
26
10
R
0
0
ASID Enable
Description
Match Flag Enable
Specifies whether or not to include the match flag value
specified by the MFI bit of this register in the match
conditions. When the specified match flag value is 1,
the condition is determined to be satisfied.
0: The match flag is not included in the match
1: The match flag is included in the match conditions.
Specifies whether or not to include the ASID specified
by the AIV bit of this register in the match conditions.
0: The ASID is not included in the match conditions;
1: The ASID is included in the match conditions.
Match Flag Specify
Specifies the match flag to be included in the match
conditions.
000000: The MF0 bit of the CCMFR register
000001: The MF1 bit of the CCMFR register
Others: Reserved (setting prohibited)
Note: The initial value is the reserved value, but when 1
ASID Specify
Specifies the ASID value to be included in the match
conditions.
R/W
conditions; thus, not checked.
thus, not checked.
25
R
0
9
0
is written into CBR1[0], MFI must be set to
000000 or 000001. And note that the channel 1 is
not hit when MFE bit of this register is 1 and MFI
bits are 000001 in the condition of CCRMF.MF1 =
0.
R/W
24
R
0
8
0
R/W
R/W
23
0
7
0
CD
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
ID
R/W
R/W
20
0
4
0
AIV
R/W
19
R
0
3
0
R/W
R/W
18
0
2
0
RW
R/W
R/W
17
0
1
0
R/W
R/W
CE
16
0
0
0
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