R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1287

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

CPU and L RAM (H'FF00 0000-H'FF3F FFFF; 4M bytes)
Physical
Address
H'FEC8 0000 to
H'FEFF FFFF
Physical
Address
H'FF00 0000
H'FF00 0004
H'FF00 0008
H'FF00 000C
H'FF00 0010
H'FF00 0014 to
H'FF00 001B
H'FF00 001C
H'FF00 0020
H'FF00 0024
H'FF00 0028
H'FF00 002C to
H'FF00 0037
H'FF00 0038
H'FF00 003C
H'FF00 0040 to
H'FF00 004F
H'FF00 0050
Register Name
Reserved
(3,670,016 bytes)
Register Name
Page table entry high
register
Page table entry low
register
Translation table base
register
TLB exception address
register
MMU control register
Reserved (8 bytes)
Cache control register
TRAPA exception register TRA
Exception event register
Interrupt event register
Reserved (12 bytes)
Queue address control
register 0
Queue address control
register 1
Reserved (16 bytes)
L memory transfer source
address register 0
Abbreviation
Abbreviation
EXPEVT

PTEH
PTEL
TTB
TEA
MMUCR

CCR
INTEVT

QACR0
QACR1

LSA0
Initial Value

Initial Value
H'xxxx xxxx
H'xxxx xxxx
H'xxxx xxxx
H'xxxx xxxx
H'0000 0000

H'0000 0000
H'0000 0000
H'xxxx xxxx

H'0000 00xx
H'0000 00xx

H'xxxx xxxx
H'xxxx xxxx
Rev.1.00 Dec. 13, 2005 Page 1235 of 1286
R/W
R/W
R/W
R/W
R/W
R/W

R/W
R/W

R/W
R/W
R/W
R/W
R/W
R/W
R/W

Access
Size

Access
Size
32
32
32
32
32

32
32
32
32

32
32

32
REJ09B0158-0100
Module

Module
MMU
MMU
MMU
MMU
MMU

Cache
Exception
Handling
Exception
Handling
Exception
Handling

Cache
Cache

L RAM
Appendix