R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 24

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 24 Multimedia Card Interface (MMCIF) ............................................. 865
24.1 Features.............................................................................................................................. 865
24.2 Input/Output Pins............................................................................................................... 866
24.3 Register Descriptions......................................................................................................... 867
24.4 Operation ........................................................................................................................... 901
24.5 MMCIF Interrupt Sources.................................................................................................. 931
24.6 Operations when Using DMA ........................................................................................... 932
24.7 Register Accesses with Little Endian Specification........................................................... 953
Section 25 Audio Codec Interface (HAC)......................................................... 955
25.1 Features.............................................................................................................................. 955
25.2 Input/Output Pins............................................................................................................... 956
25.3 Register Descriptions......................................................................................................... 957
Rev.1.00 Dec. 13, 2005 Page xxii of l
24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)................................................ 871
24.3.2 Command Start Register (CMDSTRT) ................................................................ 872
24.3.3 Operation Control Register (OPCR)..................................................................... 873
24.3.4 Card Status Register (CSTR)................................................................................ 875
24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)..................................... 877
24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) ................................... 880
24.3.7 Transfer Clock Control Register (CLKON).......................................................... 885
24.3.8 Command Timeout Control Register (CTOCR) ................................................... 886
24.3.9 Transfer Byte Number Count Register (TBCR) ................................................... 887
24.3.10 Mode Register (MODER)..................................................................................... 888
24.3.11 Command Type Register (CMDTYR).................................................................. 889
24.3.12 Response Type Register (RSPTYR)..................................................................... 890
24.3.13 Transfer Block Number Counter (TBNCR).......................................................... 894
24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD).............................. 895
24.3.15 Data Timeout Register (DTOUTR) ...................................................................... 897
24.3.16 Data Register (DR) ............................................................................................... 898
24.3.17 FIFO Pointer Clear Register (FIFOCLR) ............................................................. 899
24.3.18 DMA Control Register (DMACR) ....................................................................... 900
24.4.1 Operations in MMC Mode.................................................................................... 901
24.6.1 Operation in Read Sequence................................................................................. 932
24.6.2 Operation in Write Sequence ................................................................................ 942
25.3.1 Control and Status Register (HACCR) ................................................................. 958
25.3.2 Command/Status Address Register (HACCSAR) ................................................ 960
25.3.3 Command/Status Data Register (HACCSDR)...................................................... 962
25.3.4 PCM Left Channel Register (HACPCML)........................................................... 963
25.3.5 PCM Right Channel Register (HACPCMR) ........................................................ 965
25.3.6 TX Interrupt Enable Register (HACTIER)........................................................... 966