R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 610

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Figure 14.1 shows the block diagram of the DMAC.
Rev.1.00 Dec. 13, 2005 Page 558 of 1286
REJ09B0158-0100
(with acknowledge-
(memory mapped)
On-chip memory
[Legend]
CHCRm:
DARBn:
DARm:
DMAE:
DMAOR0 and
DMAOR1:
m:
n:
Note:
Interrupt controller
External ROM
External RAM
External I/O
External I/O
Peripheral
DREQ0 to DREQ3
DRAK0 to DRAK3
DACK0 to DACK3
module
DMA transfer acknowledge signal
ment)
0,1,2,3,4,5 for channels 0 to 5; 6,7,8,9,10,11 for channels 6 to 11
0,1,2,3 for channels 0 to 5; 6,7,8,9 for channels 6 to 11
*
DMA transfer request signal
The half-end interrupt request is available in channels 0 to 3.
DMA channel control register
DMA destination address register B
DMA destination address register
DMA Address error interrupt request
DMA operation registers 0 and 1
Peripheral
bus
DMINTm
DMAE
DMINTm
Local bus state
bus bridge
Peripheral
DDR-SDRAM
PCI controller
controller
interface
Figure 14.1 Block Diagram of DMAC
DMARS0 to
DMARS2:
DMINTm:
SARBn:
SARm:
TCRBn:
TCRm:
DMAC channels 0 to 5
DMAC channels 6 to 11
DMA extended resource selectors 0 to 2
DMA transfer end/half-end interrupt request from channel m*
DMA source address register B
DMA source address register
DMA transfer count register B
DMA transfer count register
interface
interface
Register
Request
Register
Request
Iteration
Start-up
Iteration
Start-up
Bus
Bus
control
control
control
priority
control
control
control
control
priority
control
DMARS0-2
DMAOR0
DMAOR1
CHCRm
CHCRm
SARBn
DARBn
TCRBn
SARBn
DARBn
TCRBn
SARm
DARm
TCRm
SARm
DARm
TCRm
DMAC