R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 411

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(4)
For area 3, physical address bits 28 to 26 are 011.
This area is used only for the DDR-SDRAM interface. For details, see section 12, DDR-SDRAM
Interface (DDRIF).
(5)
For area 4, physical address bits 28 to 26 are 100.
The interfaces that can be set for this area are the SRAM, burst ROM, MPX , byte control SRAM,
DDR-SDRAM and PCI local bus interfaces.
A bus width of 8, 16, or 32 bits is selectable with bits SZ in CS4BCR. When the MPX interface is
used, a bus width of 32 bits should be selected through bits SZ1 and SZ0 in CS4BCR. When the
byte control SRAM interface is used, select a bus width of 16 or 32 bits. For details, see section
11.3.2, Memory Bus Width.
When area 4 is accessed, the CS4 signal is asserted (except for DDR-SDRAM and PCI areas).
In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write
control signals WE0 to WE3 are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS4WCR can be selected. Any
number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS4 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS4WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more.
When using area 4 as the DDR-SDRAM or PCI local bus interface, set the AREASEL bit in
MMSELR. Then the CS4 signal is not asserted. When the DDR-SDRAM or PCI is used, see
section 12, DDR-SDRAM Interface (DDRIF) or section 13, PCI Controller (PCIC), respectively.
(6)
For area 5, physical address bits 28 to 26 are 101.
The interfaces that can be set for this area are the SRAM, burst ROM, PCMCIA, MPX, and DDR-
SDRAM interfaces.
Area 3
Area 4
Area 5
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 359 of 1286
REJ09B0158-0100