R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 871

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.3.9
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each
interrupt enable bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the
SIOF issues an interrupt.
Initial value:
Bit
15
14
13
12
11
R/W:
Bit:
Interrupt Enable Register (SIIER)
Bit Name
TDMAE
TCRDYE
TFEMPE
TDREQE
RDMAE
R/W
MAE
15
TD
0
R/W
TCR
DYE
14
0
R/W
MPE
TFE
13
0
Initial
Value
0
0
0
0
0
R/W
TDR
EQE
12
0
MAE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RD
11
0
RDYE
R/W
RC
10
0
Description
Transmit Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The TDREQE bit can be set as
transmit interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer
1: Enables interrupts due to transmit data transfer
Receive Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The RDREQE bit can be set as
receive interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
FULE
R/W
requests
requests
RF
9
0
REQE
R/W
RD
8
0
R/W
—
7
0
Rev.1.00 Dec. 13, 2005 Page 819 of 1286
R/W
—
6
0
Section 22 Serial I/O with FIFO (SIOF)
ERRE
R/W
SA
5
0
ERRE
R/W
FS
4
0
OVFE
R/W
TF
3
0
REJ09B0158-0100
UDFE
R/W
TF
2
0
UDFE
R/W
RF
1
0
OVFE
R/W
RF
0
0