R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 281

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.2.1
RAMCR controls the protective functions in the L memory.
Bit
31to10
9
8
7
6
5 to 0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
On-Chip Memory Control Register (RAMCR)
Bit Name
RMD
RP
IC2W
OC2W
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
0
0
0
0
All 0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R/W
R/W
R/W
R
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
On-Chip Memory Access Mode
Specifies the right of access to the L memory from the
virtual address space.
0: An access in privileged mode is allowed.
1: An access user/privileged mode is allowed.
On-Chip Memory Protection Enable
Selects whether or not to use the protective functions
using ITLB and UTLB for accessing the L memory from
the virtual address space.
0: Protective functions are not used.
1: Protective functions are used.
For further details, refer to section 9.4, L Memory
Protective Functions.
IC Two-Way Mode
For further details, refer to section 8.4.3, IC Two-Way
Mode.
OC Two-Way Mode
For further details, refer to section 8.3.6, OC Two-Way
Mode.
Reserved
These bits are always read as 0. The write value should
always be 0.
RMD
R/W
25
(An address error exception occurs in user mode.)
R
0
9
0
R/W
RP
24
R
0
8
0
IC2W OC2W
R/W
23
R
0
7
0
R/W
Rev.1.00 Dec. 13, 2005 Page 229 of 1286
22
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
Section 9 L Memory
REJ09B0158-0100
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0

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