R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 35

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ........ 535
Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus
Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus
Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus......... 540
Figure 13.15 Address Generation for Type 0 Configuration Access.......................................... 542
Figure 13.16 PCI Local Bus Power Down State Transition ....................................................... 545
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)........................................ 546
Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single)......................................... 547
Figure 13.19 Master Write Cycle in Normal Mode (Burst)........................................................ 548
Figure 13.20 Master Read Cycle in Normal Mode (Burst)......................................................... 549
Figure 13.21 Target Read Cycle in Normal Mode (Single)........................................................ 551
Figure 13.22 Target Write Cycle in Normal Mode (Single)....................................................... 552
Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) ............................ 553
Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) ........................... 554
Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping) .................. 555
Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping)..... 556
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.1 Block Diagram of DMAC ....................................................................................... 558
Figure 14.2 Round-Robin Mode (example of channel 0 to 5) .................................................... 593
Figure 14.3 Changes in Channel Priority in Round-Robin Mode
Figure 14.4 Data Flow of Dual Address Mode........................................................................... 595
Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode
Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1
Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2
Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode
Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .... 599
Figure 14.10 Bus State when Multiple Channels are Operating ................................................. 602
Figure 14.11 DMA Transfer Flowchart ...................................................................................... 603
Figure 14.12 Reload Mode Transfer........................................................................................... 605
Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 606
Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 606
Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 607
Figure 14.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 607
(example of channel 0 to 5)..................................................................................... 594
(Source: Ordinary Memory, Destination: Ordinary Memory) ................................ 596
(DREQ Low Level Detection) ................................................................................ 597
(DREQ Low Level Detection) ................................................................................ 598
(DREQ Low Level Detection) ................................................................................ 598
(Non-Byte Swapping: TBS = 0) ............................................................................ 537
(Non-Byte Swapping: TBS = 1) ............................................................................ 538
Rev.1.00 Dec. 13, 2005 Page xxxiii of l