R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 985

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• An error in a command sequence (during data reception) is detected through the CRC error
• The data remains in FIFO after the read sequence end. Set the SET[2:0] bits in DMACR to 100
• Confirm the DMA transfer end and clear the DMAEN bit in DMACR to 0.
• Set the CMDOFF bit to 1 and clear DMACR to H'00 if a CRC error (CRCERI) or a command
• Set the CMDOFF bit to 1, clear DMACR to H'00, and clear FIFO if a CRC error (CRCERI) or
Note: * In multiple block transfer, when the command sequence is ended (the CMDOFF bit is
flag or data timeout flag. When these flags are detected, set the CMDOFF bit in OPCR to 1,
issue CMD12 and suspend the command sequence.
to read all data in FIFO if necessary.
timeout error (CTERI) occurs in the command response reception.
a data timeout error (DTERI) occurs in the read data reception.
written to 1) before command response reception (CRPI), the command response may
not be received correctly. Therefore, to receive the command response correctly, the
command sequence must be continued (set the RD_CONT bit to 1) until the command
response reception ends.
Access from the DMAC to FIFO must be done in bytes or words.
Section 24 Multimedia Card Interface (MMCIF)
Rev.1.00 Dec. 13, 2005 Page 933 of 1286
REJ09B0158-0100