R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 201
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 201 of 1342
- Download datasheet (7Mb)
7.1.1
Virtual Address Space: This LSI supports a 32-bit virtual address space, and can access a 4-
Gbyte address space. The virtual address space is divided into a number of areas, as shown in
figures 7.2 and 7.3. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be
accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. When the SQMD bit in
the MMU control register (MMUCR) is 0, a 64-Mbyte space in the store queue area can be
accessed. When the RMD bit in the on-chip memory control register (RAMCR) is 1, a 16-Mbyte
space in on-chip memory area can be accessed. Accessing areas other than the U0 area, store
queue area, and on-chip memory area in user mode will cause an address error.
When the AT bit in MMUCR is set to 1 and the MMU is enabled, the P0, P3, and U0 areas can be
mapped onto any physical address space in 1-, 4-, or 64-Kbyte, or 1-Mbyte page units. By using
an 8-bit address space identifier, the P0, P3, and U0 areas can be increased to a maximum of 256.
Process 1
Address Spaces
Physical
Memory
(0)
Process 1
Process 2
Process 3
Process 1
Figure 7.1 Role of MMU
Physical
Memory
Physical
Memory
(1)
(3)
Section 7 Memory Management Unit (MMU)
Process 1
Process 1
Process 2
Process 3
Rev.1.00 Dec. 13, 2005 Page 149 of 1286
Virtual
Memory
Virtual
Memory
MMU
MMU
REJ09B0158-0100
Physical
Memory
Physical
Memory
(2)
(4)
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