R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 31

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figures
Section 1 Overview
Figure 1.1 SH7780 Block Diagram ................................................................................................ 9
Figure 1.2 SH7780 Pin Arrangement............................................................................................ 10
Figure 1.3 Physical Address Space of SH7780............................................................................. 28
Figure 1.4 Relationship between AREASEL Bits and Memory Address Map............................. 29
Section 2 Programming Model
Figure 2.1 Data Formats ............................................................................................................... 33
Figure 2.2 CPU Register Configuration in Each Processing Mode .............................................. 36
Figure 2.3 General Registers ........................................................................................................ 37
Figure 2.4 Floating-Point Registers .............................................................................................. 39
Figure 2.5 Relationship between SZ bit and Endian..................................................................... 45
Figure 2.6 Formats of Byte Data and Word Data in Register ....................................................... 47
Figure 2.7 Data Formats in Memory............................................................................................. 48
Figure 2.8 Processing State Transitions........................................................................................ 49
Section 4 Pipelining
Figure 4.1 Basic Pipelines ............................................................................................................ 73
Figure 4.2 Instruction Execution Patterns (1) ............................................................................... 75
Figure 4.2 Instruction Execution Patterns (2) ............................................................................... 76
Figure 4.2 Instruction Execution Patterns (3) ............................................................................... 77
Figure 4.2 Instruction Execution Patterns (4) ............................................................................... 78
Figure 4.2 Instruction Execution Patterns (5) ............................................................................... 79
Figure 4.2 Instruction Execution Patterns (6) ............................................................................... 80
Figure 4.2 Instruction Execution Patterns (7) ............................................................................... 81
Figure 4.2 Instruction Execution Patterns (8) ............................................................................... 82
Figure 4.2 Instruction Execution Patterns (9) ............................................................................... 83
Section 5 Exception Handling
Figure 5.1 Instruction Execution and Exception Handling......................................................... 105
Figure 5.2 Example of General Exception Acceptance Order .................................................... 106
Section 6 Floating-Point Unit (FPU)
Figure 6.1 Format of Single-Precision Floating-Point Number.................................................. 130
Figure 6.2 Format of Double-Precision Floating-Point Number ................................................ 130
Figure 6.3 Single-Precision NaN Bit Pattern .............................................................................. 133
Figure 6.4 Floating-Point Registers ............................................................................................ 136
Figure 6.5 Relation between SZ Bit and Endian......................................................................... 139
Rev.1.00 Dec. 13, 2005 Page xxix of l