R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 800

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 748 of 1286
REJ09B0158-0100
Bit
6
5
Bit Name
RIE
TE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Interrupt Enable
Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in
SCFSR is set to 1, a receive-error interrupt (ERI)
request when the ER flag in SCFSR is set to 1, and a
break interrupt (BRI) request when the BRK flag in
SCFSR or the ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request, receive-
1: Receive-data-full interrupt (RXI) request, receive-
Note: An RXI interrupt request can be cleared by
Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
Serial transmission is started when transmit data is
written to SCFTDR while the TE bit is set to 1.
0: Transmission disabled
1: Transmission enabled*
Note: SCSMR and SCFCR settings must be made, the
error interrupt (ERI) request, and break interrupt
(BRI) request disabled
error interrupt (ERI) request, and break interrupt
(BRI) request enabled
reading 1 from the RDF or DR flag in SCFSR,
then clearing the flag to 0, or by clearing the RIE
bit to 0. ERI and BRI interrupt requests can be
cleared by reading 1 from the ER, BRK, or
ORER flag in SCFSR, then clearing the flag to 0,
or by clearing the RIE and REIE bits to 0.
transmission format decided, and the transmit
FIFO reset, before the TE bit is set to 1.