R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 794

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
Since the register functions, pin functions, and interrupt requests are the same in each channel
except for the modem control, the channel number n (n = 0, 1) is omitted in the description below.
21.3.1
SCRSR is the register used to receive serial data.
The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting
with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to SCFRDR, automatically.
SCRSR cannot be directly read from and written to by the CPU.
21.3.2
SCFRDR is an 8-bit FIFO register of 64 stages that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until SCFRDR is full (64 data
bytes).
SCFRDR is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in SCFRDR, an undefined value will be
returned. When SCFRDR is full of receive data, subsequent serial data is lost.
Rev.1.00 Dec. 13, 2005 Page 742 of 1286
REJ09B0158-0100
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:




7
7




6
6




5
5




4
4




3
3




2
2




1
1




0
0