R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 623

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.3.6
TCRB are 32-bit readable/writable registers. Data to be written from the CPU to TCR is also
written to TCRB. While the half-end* function is used, TCRB are used as the initial value hold
registers to detect half-end. Also, TCRB specify the number of DMA transfers which are set in
TCR in repeat mode. TCRB specify the number of DMA transfers and are used as transfer count
counters in reload mode.
Note: * The "half-end" means the transfer is half finished.
In reload mode, the lower 8 bits (bits 7 to 0) operate as transfer count counters, values of SAR and
DAR are updated after the value of the bits 7 to 0 became 0, and then the value of the bits 23 to 16
of TCRB are loaded to the bits 7 to 0. In bits 23 to 16, set the number of transfers which starts
reloading. In reload mode, a value from H'FF (255 times) to H'01 (1 time) can be specified to the
bits 23 to 16 and 7 to 0 of TCRB, and set the same number in both bits 23 to 16 and bits 7 to 0 and
clear to H'00 in bits 15 to 8. Also, set the HIE bit in CHCR to 0 and do not use the half end
function.
The upper eight bits of TCRB (bits 31 to 24) are always read as 0, and the write value should
always be 0. The initial value of TCRB is undefined.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Transfer Count Registers B0 to B3, B6 to B9
(TCRB0 to TCRB3, TCRB6 to TCRB9)
R/W
31
15
—
—
R
R/W
—
—
30
14
R
R/W
—
—
29
13
R
R/W
—
—
28
12
R
R/W
—
—
27
11
R
R/W
—
—
26
10
R
R/W
—
—
25
R
9
R/W
—
—
24
Section 14 Direct Memory Access Controller (DMAC)
R
8
TCRB
TCRB
R/W
R/W
—
—
23
7
Rev.1.00 Dec. 13, 2005 Page 571 of 1286
R/W
R/W
—
—
22
6
R/W
R/W
—
—
21
5
R/W
R/W
—
—
20
4
R/W
R/W
—
—
19
3
REJ09B0158-0100
R/W
R/W
—
—
18
2
R/W
R/W
—
—
17
1
R/W
R/W
—
—
16
0