R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 528

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
(25) PCI Power Management Capability Register (PCIPMC)
PCIPMCS is a 16-bit register that provides information on the capabilities of the power
management related functions. For details, refer to “PCI Bus Power Management Interface
Specification Revision 1.1 Chapter 3 PCI Power Management Interface”. This register must be set
during initializing the PCIC registers (PCICR.CFINIT = 0).
Rev.1.00 Dec. 13, 2005 Page 476 of 1286
REJ09B0158-0100
Initial value:
Bit
15 to 11 PMCS
10
9
PCI R/W:
SH R/W:
Bit:
Bit Name
D2S
D1S
15
R
R
0
14
R
R
0
PMCS
Initial
Value
00000
0
0
13
R
R
0
12
R
R
0
R/W
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
11
R
R
0
D2S
R/W
10
R
0
Description
PME_SUPPORT
This 5-bit field indicates the power states in which the
function may assert PME. A value of 0b for any bit
indicates that the function is not capable of asserting
the PME signal while in that power state.
Bit11: xxxx1 - PME can be asserted from D0
Bit12: xxx1x - PME can be asserted from D1
Bit13: xx1xx - PME can be asserted from D2
Bit14: x1xxx - PME can be asserted from D3 hot
Bit15: 1xxxx - PME can be asserted from D3 cold
Note: This LSI dose not have the PME pin.
When this bit is 1, This function supports the D2
power management state. When the D2 power
management state is not supported, this bit is read as
0.
When this bit is 1, This function supports the D1
power management state. When the D1 power
management state is not supported, this bit is read as
0.
D1S
R/W
R
0
9

R
R
8
0

R
R
7
0

R
R
6
0
DSI
R
R
5
0

R
R
4
0
PMEC
R/W
R
3
1
R/W
R
2
0
PMV
R/W
R
1
1
R/W
R
0
0