R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 737

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit Name
TE3
TE2
TE1
TE0
IOE3
IOE2
IOE1
IOE0
ICE3
ICE2
ICE1
ICE0
—
IEE1
IEE0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Channel 3 to 0 timer enable
Enables the counting of each of the 16-bit counters. If
these bits are inactive when operating in timer mode or
in counter mode, the counters are reset to 0.
In updown-counter mode, channel 1 needs to be
disabled (TE1 = 0).
0: Counting disabled; counter will be reset to H'0000
1: Counter is incremented
n = 3 to 0
Channel 3 to 0 Interrupt Overflow Enable
These bits enable an interrupt to be generated when
the relevant IOn bit is set in CMTIRQS register.
0: Interrupt generation disabled
1: Interrupt generation enabled
n = 3 to 0
Channel 3 to 0 Interrupt Compare Enable
These bits enable an interrupt to be generated when
the relevant ICn bit is set in the CMTIRQS register.
0: Interrupt generation disabled
1: Interrupt generation enabled
n = 3 to 0
Reserved
These bits are always read as 0. The write value should
always be 0.
Channel 1 to 0 Interrupt Edge Enable
These bits enable an interrupt to be generated when
the relevant IEn bit is set in CMTIRQS register.
0: Interrupt generation disabled
1: Interrupt generation enabled
When a channel is in output compare mode, the
corresponding IEEn has to be set to 0.
n = 1, 0
Rev.1.00 Dec. 13, 2005 Page 685 of 1286
Section 19 Compare Match Timer (CMT)
REJ09B0158-0100