R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 907

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
8
7
6
5
4
Bit Name
TXEM
RXFU
RXHA
RXEM
RXOO
Initial
Value
1
0
0
1
0
R/W
R
R
R
R
R/W*
Description
Transmit FIFO Empty Flag
This status flag is enabled only to operation in FIFO
mode. The flag is set to 1 when the transmit FIFO is
empty of data to transmit. It is cleared to 0 when more
data is written to the transmit FIFO.
If TXEM = 1 and TEIE = 1 then the interrupt is
generated.
Receive FIFO Full Flag
This status flag is enabled only to operation in FIFO
mode. The flag is set to 1 when the receive FIFO is full
of received bytes and cannot accept any more. It is
cleared to 0 when data is read out of the receive FIFO.
If RXFU = 1 and RFIE = 1 then the interrupt is
generated.
Receive FIFO Halfway Flag
This status flag is enabled only to operation in FIFO
mode. The flag is set to 1 when the receive FIFO
reaches the halfway point, that is, it has 4 bytes of data
and 4 spaces for more data. This flag is cleared to 0
when the receive data is read from receive FIFO and
the FIFO level becomes under 4 bytes (halfway point).
It remain set to 1 until cleared to 0 regardless of the
subsequent FIFO levels.
If RXHA = 1 and RHIE = 1 then the interrupt is
generated.
Receive FIFO Empty Flag
This status flag is enabled only to operation in FIFO
mode. The flag is set to 1 when the receive FIFO is
empty of received data. It is cleared to 0 when more
data is received into to the receive FIFO.
If RXEM = 0 and RNIE = 1 then the interrupt is
generated.
Receive Buffer Overrun Occurred Flag
This status flag is set to 1 when new data has been
received but the previous received data has not been
read from SPRBR. The previously received data will not
be overwritten by the newly received data. The RXOO
flag remain set to 1 until writing a 0 to its bit position.
If RXOO = 1 and ROIE = 1 then the interrupt is
generated.
Section 23 Serial Protocol Interface (HSPI)
Rev.1.00 Dec. 13, 2005 Page 855 of 1286
REJ09B0158-0100