R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 916

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 23 Serial Protocol Interface (HSPI)
23.4.5
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI software reset is
generated. The receive and transmit FIFO pointers can be initialized by the HSPI software reset.
The data transmission after the HSPI software reset should protect transmitting and receiving
protocol of HSPI, and please perform it from the first. A guarantee of operation is not offered
other than it.
While the master device is not transferring data and the HSPI is in slave mode, the HSPI software
reset should be generated before asserting the HSPI_CS. This prevent the HSPI from receiving an
erroneous data.
23.4.6
SPCR also allows the user to define the shift timing for transmit data and polarity. The FBS bit in
SPCR allows selection between two different transfer formats. The MSB or LSB is valid on the
falling edge of HSPI_CS. The CLKP bit in SPCR allows for control of the polarity select block
which controls which edges of HSPI_CLK shift and sample data in the master and slave.
23.4.7
The master and slave can be considered linked together as a circular shift register synchronized
with HSPI_CLK. The transmit byte from the master is replaced with the receive byte from the
slave in eight HSPI_CLK cycles. Both the transmit and receive functions are double buffered to
allow for continuous reads and writes. When FIFO mode is enabled eight entry FIFOs are
available for both transmit and receive data.
Rev.1.00 Dec. 13, 2005 Page 864 of 1286
REJ09B0158-0100
HSPI Software Reset
Clock Polarity and Transmit Control
Transmit and Receive Routines
sck_cycle
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
HSPI_TX
HSPI_RX
HSPI_RX
Figure 23.4 Timing Conditions when FBS = 1
*
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
LSB
8
LSB