R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 398

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 346 of 1286
REJ09B0158-0100
Bit
3 to 0
Bit Name
IW[3:0]
Initial
Value
1111
R/W
R/W
Description
Insert Wait Cycle
Specify the number of wait cycles to be inserted.
•
•
When the SRAM interface, byte control SRAM
interface, burst ROM interface (first data cycle only),
or PCMCIA interface is selected, the following
cycles are inserted. The external wait cycle insertion
by using the RDY pin monitor cannot be used when
no cycle inserted is selected.
When the MPX interface is selected, the following
cycles are inserted by the setting value of IW [2:0]
and then IW3 setting is invalid. And the external wait
cycle insertion by using the RDY pin monitor can be
used in all the following settings.
0000: No cycle inserted 1000: 8 cycles inserted
0001: 1 cycle inserted
0010: 2 cycles inserted 1010: 11 cycles inserted
0011: 3 cycles inserted 1011: 13 cycles inserted
0100: 4 cycles inserted 1100: 15 cycles inserted
0101: 5 cycles inserted 1101: 17 cycles inserted
0110: 6 cycles inserted 1110: 21 cycles inserted
0111: 7 cycles inserted 1111: 25 cycles inserted
IW2 specifies the number of wait cycle to be
inserted into second data or after.
0: No cycle inserted
1: 1 cycle inserted
IW[1:0] specify the number of wait cycles to be
inserted into first data.
00: 1 cycle inserted into read cycle and no cycle
01: 1 cycle inserted into read cycle and 1 cycle
10: 2 cycles inserted into read cycle and 2 cycles
11: 3 cycles inserted into read cycle and 3 cycles
inserted into write cycle
inserted into write cycle
inserted into write cycle
inserted into write cycle
1001: 9 cycles inserted