R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 903

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23.2
The input/output pins of the HSPI is shown in table 23.1.
Table 23.1 Pin Configuration
Note: These pins are multiplexed with the SCIF channel 0, FLCTL, GPIO and mode control pins.
23.3
Table 23.2 shows the HSPI register configuration. Table 23.3 shows the register states in each
processing mode.
Table 23.2 Register Configuration
Note: To clear the flag, only 0s are written to bits 4 and 3.
Table 23.3 Register States of HSPI in Each Processing Mode
Pin Name
HSPI_CLK
HSPI_TX
HSPI_RX
HSPI_CS
Register Name
Control register
Status register
System control register
Transmit buffer register
Receive buffer register
Register Name
Control register
Status register
System control register
Transmit buffer register
Receive buffer register
Input/Output Pins
Register Descriptions
Function
Serial bit clock pin
Transmit data pin
Receive data pin
Chip select pin
Abbrev. R/W
SPCR
SPSR
SPSCR
SPTBR
SPRBR
Abbrev.
SPCR
SPSR
SPSCR
SPTBR
SPRBR
Power-on Reset
by PRESET
Pin/WDT/H-UDI
H'0000 0000
H'0000 0020
H'0000 0040
H'0000 0000
H'0000 0000
R/W
R/W* H'FFE5 0004
R/W
R/W
R
I/O
Input/Output
Output
Input
Input/Output
P4 Address
H'FFE5 0000
H'FFE5 0008
H'FFE5 000C
H'FFE5 0010
Manual Reset by
WDT/Multiple
Exception
H'0000 0000
H'xxxx xx20
H'0000 0040
H'0000 0000
H'0000 0000
Section 23 Serial Protocol Interface (HSPI)
Rev.1.00 Dec. 13, 2005 Page 851 of 1286
Description
Clock input/output
Transmit data output
Receive data input
Chip select
Area 7 Address Size
H'1FE5 0000
H'1FE5 0004
H'1FE5 0008
H'1FE5 000C
H'1FE5 0010
Sleep by
SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
REJ09B0158-0100
32
32
32
32
32
Module
Standby
Retained
Retained
Retained
Retained
Retained
Sync
Clock
Pck
Pck
Pck
Pck
Pck