R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 305
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 10.4 Register States in Each Operating Mode
Name
Interrupt control register 0
Interrupt control register 1
Interrupt priority register
Interrupt source register
Interrupt mask register 0
Interrupt mask register 1
Interrupt mask register 2
Interrupt mask clear register 0 INTMSKCLR0 H'0000 0000
Interrupt mask clear register 1 INTMSKCLR1 H'0000 0000
Interrupt mask clear register 2 INTMSKCLR2 H'0000 0000
NMI flag control register
User interrupt mask level
register
On-chip module interrupt
priority registers
Interrupt source register (not
affected by the mask state)
Interrupt source register
(affected by the mask state)
Interrupt mask register
Interrupt mask clear register
INTPRI
NMIFCR
INT2MSKR
Abbreviation
ICR0
ICR1
INTREQ
INTMSK0
INTMSK1
INTMSK2
USERIMASK
INT2PRI0
INT2PRI1
INT2PRI2
INT2PRI3
INT2PRI4
INT2PRI5
INT2PRI6
INT2PRI7
INT2A0
INT2A1
INT2MSKCR
H'0000 0000
H'0000 0000
H'xxxx xxxx
H'FFFF FFFF
Power-on Reset
by PRESET
Pin/WDT/H-UDI
H'x000 0000*
H'0000 0000
H'0000 0000
H'FF00 0000
H'FF00 0000
H'0000 0000
H'x000 0000*
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
Rev.1.00 Dec. 13, 2005 Page 253 of 1286
Manual Reset by
WDT/Multiple
Exception
H'x000 0000*
H'0000 0000
H'0000 0000
H'0000 0000
H'FF00 0000
H'FF00 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'x000 0000*
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'xxxx xxxx
H'0000 0000
H'FFFF FFFF
H'0000 0000
Section 10 Interrupt Controller (INTC)
Sleep by SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
REJ09B0158-0100
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