R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 877
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 877 of 1342
- Download datasheet (7Mb)
22.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame. SICDAR can be specified only when the FL bits in SIMDR are specified as B'1xxx (x:
don't care).
Bit
7
6 to 4
3 to 0
Initial value:
Bit
15
14 to 12 —
R/W:
Bit:
Bit Name
RDRE
—
RDRA[3:0]
Bit Name
CD0E
CD0E
R/W
15
0
14
—
R
0
13
—
R
0
Initial
Value
0
All 0
0000
Initial
Value
0
All 0
12
—
R
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R
11
0
R/W
CD0
10
0
A[3:0]
Receive Right-Channel Data Enable
Receive Right-Channel Data Assigns 3 to 0
Control Channel 0 Data Enable
Description
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Specify the position of right-channel data in a receive
frame as 0000 (0) to 1110 (14).
1111: Setting prohibited
•
Description
0: Disables transmission and reception of control
1: Enables transmission and reception of control
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
channel 0 data
channel 0 data
9
0
Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
R/W
8
0
CD1E
R/W
7
0
Rev.1.00 Dec. 13, 2005 Page 825 of 1286
—
R
6
0
Section 22 Serial I/O with FIFO (SIOF)
—
R
5
0
—
R
4
0
R/W
3
0
REJ09B0158-0100
R/W
CD1
2
0
A[3:0]
R/W
1
0
R/W
0
0
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