R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 633

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.8
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status. DMAOR 0 is for channel 0 to 5, and
DMAOR1 is for channel 6 to11.
Initial value:
Bit
15, 14
13, 12
11, 10
R/W:
Bit:
DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)
Bit Name
CMS[1:0]
15
R
0
14
R
0
R/W
CMS[1:0]
13
Initial
Value
All 0
00
0
All 0
R/W
12
0
R/W
R
R/W
R
11
R
0
10
R
0
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
Cycle Steal Mode Select 1, 0
Select either normal mode or intermittent mode in cycle
steal mode.
It is necessary that all channels 0 to 5 (DMAOR0) or 6
to 11 (DMAOR1) bus modes are set to cycle steal mode
to make valid intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
PR[1:0]
9
0
Issues a bus request after waiting 16 Bck clocks
and executes one DMA transfer.
Issues a bus request after waiting 64 Bck clocks
and executes one DMA transfer.
R/W
Section 14 Direct Memory Access Controller (DMAC)
8
0
R
7
0
Rev.1.00 Dec. 13, 2005 Page 581 of 1286
R
6
0
R
5
0
R
4
0
R
3
0
R/(W)*R/(W)* R/W
REJ09B0158-0100
AE
2
0
NMIF DME
1
0
0
0

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