R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 540

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 PCI Controller (PCIC)
(6)
PCIIR records the source of an interrupt.
When multiple interrupts occur, only the first source is registered.
When an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this
register, however, no interrupt occurs.
Rev.1.00 Dec. 13, 2005 Page 488 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 15 
14
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Interrupt Register (PCIIR)
Bit:
Bit:
Bit Name
TTADI
31
15
R
R
R
R
0
0
R/WC
TTA
30
14
DI
R
R
R
0
0
Initial
Value
All 0
0
29
13
R
R
R
R
0
0
28
12
R
R
R
R
0
0
R/W
SH: R
PCI: R
SH: R/WC
PCI: R
27
11
R
R
R
R
0
0
26
10
R
R
R
R
0
0
R/WC
TMT
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Target-Abort Interrupt
Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
A target-abort is detected as an illegal byte enable
when the lower two bits (bits 1 and 0) of the address
and the byte enable do not match during an I/O
transfer (target).
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
25
OI
R
R
R
9
0
0
R/WC
MDEI
24
R
R
R
0
8
0
R/WC
APE
23
DI
R
R
R
0
7
0
R/WC
SE
22
DI
R
R
R
0
6
0
R/WC
DPEI
TW
21
R
R
R
0
5
0
R/WC
DPEI
TR
20
R
R
R
0
4
0
R/WC
TAD
19
IM
R
R
R
0
3
0
R/WC
MAD
18
IM
R
R
R
0
2
0
R/WC
MW
PDI
17
R
R
R
0
1
0
R/WC
MRD
PEI
16
R
R
R
0
0
0

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