R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 54

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
Table 1.1
Rev.1.00 Dec. 13, 2005 Page 2 of 1286
REJ09B0158-0100
Item
LSI
CPU
SH7780 Features
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating frequency: 400 MHz
Performance: 720MIPS, 2.8 GFLOPS
Voltage: 1.25 V (internal), 2.5 V (DDR-SDRAM interface), 3.3 V (I/O)
Superscalar architecture: Parallel execution of two instructions
Packages: 449-pin BGA (Size: 21 × 21 mm, pin pitch: 0.8 mm)
Local bus interface (External bus):
 Separate 26-bit address and 32-bit data buses
 External bus frequency: 100 MHz
DDR-SDRAM bus interface (External bus):
 Separate 14-bit address and 32-bit data buses
 External bus frequency: 133 M or 160 MHz (DDR266/320)
PCI bus interface (External bus):
 32-bit address/data multiplexing
 External bus frequency: 33M or 66 MHz
Renesas Technology original architecture
32-bit internal data bus
General-register files:
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Seven 32-bit control registers
 Four 32-bit system registers
RISC-type instruction set (upward compatible with the SH-1, SH-2, SH-3
and SH-4 microcomputers)
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instructions
 Instructions executed with conditions
 Instruction set based on the C language
Super scalar which executes two instructions simultaneously including
the FPU
Instruction execution time: Two instructions per cycle (max)
Virtual address space: 4 Gbytes
Space identifier ASID: 8 bits, 256 virtual address spaces
On-chip multiplier
Seven-stage pipeline