R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 56

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Rev.1.00 Dec. 13, 2005 Page 4 of 1286
REJ09B0158-0100
Item
Memory
management
unit (MMU)
Cache memory
L memory
SuperHyway
memory
Features
4 Gbytes of physical address space, 256 address space identifiers
(address space identifier ASID: 8 bits)
Supports single virtual memory mode and multiple virtual memory mode
Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, or 1 Mbyte
4-entry full associative TLB for instructions
64-entry full associative TLB for instructions and operands
Supports software selection of replacement method and random-counter
replacement algorithms
Contents of TLB are directly accessible through address mapping
Instruction cache (IC)
 32-Kbyte 4-way set associative
 32-byte block length
Operand cache (OC)
 32-Kbyte 4-way set associative
 32-byte block length
 Selectable write method (copy-back or write-through)
Storage queue (32 bytes × 2 entries)
Three independent read/write ports
 Instruction fetch access by the CPU
 8-/16-/32-/64-bit operand access by the CPU
 8-/16-/32-/64-bit and 16-/32-byte access by the SuperHyway bus
16-Kbyte capacity
Supports memory protective functions during CPU accesses
8-/16-/32-/64-bit and 16-/32-byte access from the SuperHyway bus
master
32-Kbyte capacity
master

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