R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 929
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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24.3.5
The INTCR registers enable or disable interrupts.
• INTCR0
Bit
7
6
5
4
3
Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)
Bit Name
FEIE
FFIE
DRPIE
DTIE
CRPIE
Initial value:
Initial
Value
0
0
0
0
0
R/W:
Bit:
FEIE
R/W
7
0
R/W
R/W
R/W
R/W
R/W
R/W
FFIE DRPIE DTIE CRPIE CMDIE
R/W
6
0
Description
FIFO Empty Interrupt Flag Setting Enable
0: Disables FIFO empty interrupt (disables FEI flag
1. Enables FIFO empty interrupt (enables FEI flag
FIFO Full Interrupt Flag Setting Enable
0: Disables FIFO full interrupt (disables FFI flag
1: Enables FIFO full interrupt (enables FFI flag setting).
Data Response Interrupt Flag Setting Enable
0: Disables data response interrupt (disables DPRI flag
1: Enables data response interrupt (enables DPRI flag
Data Transfer End Interrupt Flag Setting Enable
0: Disables data transfer end interrupt (disables DTI
1: Enables data transfer end interrupt (enables DTI flag
Command Response Receive End Interrupt Flag
Setting Enable
0: Disables command response receive end interrupt
1: Enables command response receive end interrupt
R/W
5
0
setting).
setting).
setting).
(disables CRPI flag setting).
(enables CRPI flag setting).
setting).
setting).
setting).
flag setting).
R/W
4
0
R/W
Section 24 Multimedia Card Interface (MMCIF)
3
0
Rev.1.00 Dec. 13, 2005 Page 877 of 1286
R/W
2
0
R/W
DBS
YIE
1
0
BTIE
R/W
0
0
REJ09B0158-0100
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