R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 465

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
45
44
43 to 35 
34
33
32 to 29 
Bit Name
PCKE
SELFS
RMODE
0
Initial
Value
0
0
All 0
0
All 0
R/W
R
R/W
R
R
R/W
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Power Down
This bit controls a low power consumption mode in
which the CKE pin is set low to place the DDR-SDRAM
in “power-down mode” whenever the DDR-SDRAM is
not being accessed (whether it is in the idle state or
bank active state). When the PCKE bit is set to 1, the
DDR-SDRAM enters this power down mode. For
details, see section 12.5.5 (2), Power-Down Mode
(when CKE Goes Low). Note that the SMS bits in SCR
should be set so that the CKE pin is enabled when the
SDRAM is in its initial state.
Reserved
These bits are always read as 0. The write value
should always be 0.
Self-Refresh Decision
Indicates whether the DDR-SDRAM is or is not in the
self-refresh state.
0: Not self-refresh state
1: Self-refresh state
Refresh Mode Select
Specifies whether the DDR-SDRAM is set to auto-
refresh mode or to self-refresh mode. This bit is only
valid if the DRE bit in MIM is set to 1.
0: Auto-refresh mode
1: Self-refresh mode
Reserved
These bits are always read as 0. The write value
should always be 0.
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 413 of 1286
REJ09B0158-0100

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