R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 179

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.7
1. Return from exception handling
2. If an exception or interrupt occurs when BL bit in SR = 1
3. SPC when an exception occurs
4. RTE instruction delay slot
A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set
B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the
A. Exception
B. Interrupt
A. Re-execution type exception
B. Completion type exception or interrupt
A. The instruction in the delay slot of the RTE instruction is executed only after the value
B. The user break is not accepted by the instruction in the delay slot of the RTE instruction.
the BL bit in SR to 1 before restoring them.
SSR contents are saved in SR, and branch is made to the SPC address to return from the
exception handling routine.
When an exception other than a user break occurs, a manual reset is executed. The value in
EXPEVT at this time is H'00000020; the SPC and SSR contents are undefined.
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after
the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)
occurs, it can be held pending or accepted according to the setting made by software.
In sleep mode, however, an interrupt is accepted even if the BL bit in SR is set to 1.
The PC value for the instruction at which the exception occurred is set in SPC, and the
instruction is re-executed after returning from the exception handling routine. If an
exception occurs in a delay slot instruction, however, the PC value for the delayed branch
instruction is saved in SPC regardless of whether or not the preceding delay slot instruction
condition is satisfied.
The PC value for the instruction following that at which the exception occurred is set in
SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value
for the branch destination is saved in SPC.
saved in SSR has been restored to SR. The acceptance of the exception related to the
instruction access is determined depending on SR before restoring, while the acceptance of
other exceptions is determined depending on the processing mode by SR after restoring or
the BL bit. The completion type exception is accepted before branching to the destination
of RTE instruction. However, if the re-execution type exception is occurred, the operation
cannot be guaranteed.
Usage Notes
Rev.1.00 Dec. 13, 2005 Page 127 of 1286
Section 5 Exception Handling
REJ09B0158-0100