R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 349

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

upward compatibility with the “level-sense IRQ mode” of current SH-4 products (here, too, the
detection of high or low levels is selectable).
Note: When high-or low-level detection is selected, once the interrupt request has been detected,
When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically modified to the level of an accepted interrupt. When the INTMU bit is cleared to 0,
the IMASK value in SR is not affected by the acceptance of an interrupt.
10.4.3
IRL interrupts are input as combinations of levels on pins IRQ/IRL7 to IRQ/IRL4 or IRQ/IRL3 to
IRQ/IRL0. The priority level is the value indicated by the levels (active low) on pins IRQ/IRL7 to
IRQ/IRL4 or IRQ/IRL3 to IRQ/IRL0. The low level on all pins from IRQ/IRL7 to IRQ/IRL4 or
IRQ/IRL3 to IRQ/IRL0 corresponds to the highest-level interrupt request (interrupt priority level
15), and the high level on all pins corresponds to no interrupt request (interrupt priority level 0).
Figure 10.2 shows an example of IRL interrupt connection, and table 10.11 shows the
correspondence between the combinations of levels on the IRL pins and priority.
the INTC holds the interrupt request as an interrupt source in INTREQ even if the level on
the IRQ interrupt pin has been changed and canceled. The interrupt source is held until the
CPU accepts any interrupt request (IRQ or not) or the corresponding interrupt mask bit is
set to 1. Moreover, when the holding function is selected by clearing the LSH bit in ICR0
to 0, the interrupt request is held in the detection circuit. In this case, clearing of the
interrupt request in the exception handling routine must be followed by clearing of the
interrupt source setting being held in INTREQ. For details, see section 10.7 Usage Notes.
IRL Interrupts
Interrupt
requests
Interrupt
requests
Figure 10.2 Example of IRL Interrupt Connection
. .
.
. .
.
Priority
encoder
Priority
encoder
IRL3 to IRL0
IRL7 to IRL4
Rev.1.00 Dec. 13, 2005 Page 297 of 1286
IRQ/IRL3 to
IRQ/IRL7 to
IRQ/IRL0
IRQ/IRL4
Section 10 Interrupt Controller (INTC)
SH7780
REJ09B0158-0100