R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 797

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
5
4
Bit Name
PE
O/E
Initial
Value
0
0
R/W
R/W
R/W
Description
Parity Enable
In asynchronous mode, selects whether or not parity bit
addition is performed in transmission, and parity bit
checking is performed in reception. In clocked
synchronous mode, parity bit addition and checking is
disabled regardless of the PE bit setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or
Parity Mode
Selects either even or odd parity for use in parity
addition and checking. In asynchronous mode, the O/E
bit setting is only valid when the PE bit is set to 1,
enabling parity bit addition and checking. In clocked
synchronous mode or when parity addition and
checking is disabled in asynchronous mode, the O/E bit
setting is invalid.
0: Even parity
1: Odd parity
When even parity is set, parity bit addition is performed
in transmission so that the total number of 1-bits in the
transmit character plus the parity bit is even. In
reception, a check is performed to see if the total
number of 1-bits in the receive character plus the parity
bit is even.
When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1-bits in the
transmit character plus the parity bit is odd. In
reception, a check is performed to see if the total
number of 1-bits in the receive character plus the parity
bit is odd.
Section 21 Serial Communication Interface with FIFO (SCIF)
odd) specified by the O/E bit is added to
transmit data before transmission. In
reception, the parity bit is checked for the
parity (even or odd) specified by the O/E bit.
Rev.1.00 Dec. 13, 2005 Page 745 of 1286
REJ09B0158-0100