R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 87

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Floating-Point Registers and System Registers Related to FPU: There are thirty-two floating-
point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0–XF15 can be assigned to either
of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1).
FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating-
point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–
XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix
XMTRX.
System registers related to the FPU comprise the floating-point communication register (FPUL)
and the floating-point status/control register (FPSCR). These registers are used for communication
between the FPU and the CPU, and the exception handling setting.
Register values after a reset are shown in table 2.1.
Table 2.1
Note:
The CPU register configuration in each processing mode is shown in figure 2.2.
User mode and privileged mode are switched by the processing mode bit (MD) in the status
register.
Type
General registers R0_BANK0 to R7_BANK0,
Control registers
System registers
Floating-point
registers
*
Initialized by a power-on reset and manual reset.
Initial Register Values
Registers
R0_BANK1 to R7_BANK1,
R8 to R15
SR
GBR, SSR, SPC, SGR, DBR Undefined
VBR
MACH, MACL, PR
PC
FR0 to FR15, XF0 to XF15,
FPUL
FPSCR
Initial Value*
Undefined
MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,
IMASK = B'1111, reserved bits = 0,
others = undefined
H'00000000
Undefined
H'A0000000
Undefined
H'00040001
Rev.1.00 Dec. 13, 2005 Page 35 of 1286
Section 2 Programming Model
REJ09B0158-0100