R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 217

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.2.7
When the specific resource is changed, IRMCR controls whether the instruction fetch is performed
again for the next instruction. The specific resource means the part of control registers, TLB, and
cache.
In the initial state, the instruction fetch is performed again for the next instruction after changing
the resource. However, the CPU processing performance will be lowered because the instruction
fetch is performed again for the next instruction every time the resource is changed. Therefore, it
is recommended that each bit in IRMCR is set to 1 and the specific instruction should be executed
after all necessary resources have been changed prior to execution of the program which uses
changed resources.
For details on the specific sequence, see descriptions in each resource.
Initial value:
Initial value:
Bit
31 to 5
4
3
R/W:
R/W:
Bit:
Bit:
Instruction Re-Fetch Inhibit Control Register (IRMCR)
Bit Name

R2
R1
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R/W
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Re-Fetch Inhibit 2 after Register Change
When MMUCR, PASCR, CCR, PTEH, or RAMCR is
changed, this bit controls whether re-fetch is
performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit 1 after Register Change
When a register allocated in addresses H'FF200000 to
H'FF2FFFFF is changed, this bit controls whether re-
fetch is performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
Section 7 Memory Management Unit (MMU)
Rev.1.00 Dec. 13, 2005 Page 165 of 1286
22
R
R
0
6
0
21
R
R
0
5
0
R/W
R2
20
R
0
4
0
R/W
R1
19
R
0
3
0
REJ09B0158-0100
R/W
18
LT
R
0
2
0
R/W
MT
17
R
0
1
0
R/W
MC
16
R
0
0
0