R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 27

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

28.3 Usage Example ................................................................................................................ 1097
Section 29 User Break Controller (UBC) ........................................................1101
29.1 Features............................................................................................................................ 1101
29.2 Register Descriptions ....................................................................................................... 1103
29.3 Operation Description ...................................................................................................... 1120
29.4 User Break Debugging Support Function ........................................................................ 1127
29.5 User Break Examples....................................................................................................... 1128
28.2.19 Port G Data Register (PGDR)............................................................................. 1084
28.2.20 Port H Data Register (PHDR)............................................................................. 1085
28.2.21 Port J Data Register (PJDR) ............................................................................... 1085
28.2.22 Port K Data Register (PKDR)............................................................................. 1086
28.2.23 Port L Data Register (PLDR).............................................................................. 1086
28.2.24 Port M Data Register (PMDR) ........................................................................... 1087
28.2.25 Port E Pull-Up Control Register (PEPUPR) ....................................................... 1087
28.2.26 Port H Pull-Up Control Register (PHPUPR) ...................................................... 1088
28.2.27 Port J Pull-Up Control Register (PJPUPR)......................................................... 1089
28.2.28 Port K Pull-Up Control Register (PKPUPR) ...................................................... 1090
28.2.29 Port M Pull-Up Control Register (PMPUPR)..................................................... 1091
28.2.30 Input-Pin Pull-Up Control Register 1 (PPUPR1)................................................ 1092
28.2.31 Input-Pin Pull-Up Control Register 2 (PPUPR2)................................................ 1093
28.2.32 On-chip Module Select Register (OMSELR) ..................................................... 1094
28.3.1 Port Output Function .......................................................................................... 1097
28.3.2 Port Input function .............................................................................................. 1098
28.3.3 On-chip Module Function................................................................................... 1099
29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......................... 1105
29.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......................... 1111
29.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)............................ 1113
29.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)........... 1114
29.2.5 Match Data Setting Register 1 (CDR1) .............................................................. 1115
29.2.6 Match Data Mask Setting Register 1 (CDMR1) ................................................. 1116
29.2.7 Execution Count Break Register 1 (CETR1) ...................................................... 1117
29.2.8 Channel Match Flag Register (CCMFR) ............................................................ 1118
29.2.9 Break Control Register (CBCR) ......................................................................... 1119
29.3.1 Definition of Words Related to Accesses ........................................................... 1120
29.3.2 User Break Operation Sequence ......................................................................... 1121
29.3.3 Instruction Fetch Cycle Break ............................................................................ 1122
29.3.4 Operand Access Cycle Break.............................................................................. 1123
29.3.5 Sequential Break ................................................................................................. 1124
29.3.6 Program Counter Value to be Saved................................................................... 1126
Rev.1.00 Dec. 13, 2005 Page xxv of l